Fast Fourier transform (FFT) of large number of samples requires hugehardware resources of field programmable gate arrays (FPGA), which needs morearea and power. In this paper, we present an area efficient architecture of FFTprocessor that reuses the butterfly elements several times. The FFT processoris simulated using VHDL and the results are validated on a Virtex-6 FPGA. Theproposed architecture outperforms the conventional architecture of a $N$-pointFFT processor in terms of area which is reduced by a factor of $log_N 2$ withnegligible increase in processing time.
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机译：大量样本的快速傅里叶变换（FFT）需要现场可编程门阵列（FPGA）的大量硬件资源，这需要更多的面积和功能。在本文中，我们提出了一种高效的FFT处理器架构，该架构可多次重复使用蝶形元素。使用VHDL对FFT处理器进行了仿真，并在Virtex-6 FPGA上验证了结果。所提出的架构在面积方面优于$ N $点FFT处理器的常规架构，该架构减少了$ log_N 2 $的因子，而处理时间却可以忽略不计。
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